1. Field of the Invention
This invention relates generally to the art of microelectronic integrated circuits. More specifically, this invention relates to the art of erasing microelectronic flash Electrically Erasable Programmable Read-Only Memory (EEPROM) devices. Even more specifically, this invention relates to a method of erasing microelectronic flash Electrically Erasable Programmable Read-Only Memory devices that provides a reduced constant electric field during erase.
2. Discussion of the Related Art
A microelectronic flash or block erase Electrically Erasable Programmable Read-Only Memory (Flash EEPROM) includes an array of cells that can be independently programmed and read. The size of each cell and thereby the memory are made small by omitting transistors known as select transistors that enable the cells to be erased independently. As a result, all of the cells are erased together as a block.
A memory of this type includes individual Metal-Oxide-Semiconductor (MOS) field effect transistor memory cells, each of which includes a source, a drain, a floating gate and a control gate to which various voltages are applied to program the cell with a binary 1 or 0, or to erase all of the cells as a block.
The cells are connected in an array of rows and columns, with the control gates of the cells in a row being connected to a respective wordline and the drains of the cells in a column being connected to a respective bitline. The sources of the cells are connected together. This arrangement is known as a NOR memory configuration.
A cell is programmed by applying a voltage, typically 9 volts to the control gate, applying a voltage of approximately 5 volts to the drain and grounding the source, which causes hot electrons to be injected from a drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative change therein which increases the threshold voltage of the cell to a value in excess of approximately 4 volts.
A cell is read by applying typically 5 volts to the control gate, applying 1 volt to the bitline to which the drain is connected, grounding the source, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (4 volts), the bitline current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (2 volts), the control gate voltage will enhance the channel, and the bitline current will be relatively high.
A cell can be erased in several ways. In one arrangement, applying a relatively high voltage, typically 12 volts, to the source, grounding the control gate and allowing the drain to float erase a cell. This causes the electrons that were injected into the floating gate during programming to undergo Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. Applying a negative voltage on the order of minus 10 volts to the control gate, applying 5 volts to the source and allowing the drain to float can also erase a cell. Another method of erasing a cell is by applying 5V to the P-well and minus 10 volts to the control gate while allowing the source/drain to float.
Significant problems exist during erase that result in decreased reliability of the memory cell. During a negative gate edge erase procedure some current flows from the double diffused source region into the substrate when the source junction is reverse biased during erase. This current is referred to as band-to-band tunneling current. The magnitude of the band-to-band tunneling current depends upon the magnitude reverse bias voltage applied to the source region. With the control gate biased at a negative voltage, the hole component (called "hot holes") of the band-to-band tunneling current tends to follow the electric field and bombard the semiconductor dielectric interface between the substrate and the tunnel oxide. These hot holes can damage the interface by generating undesirable interface states. In addition, some of these hot holes may actually have enough energy to be injected into the tunnel oxide, where they are trapped. These trapped hot holes degrade the performance of the memory device. The negative control gate voltage technique for erasing memory cells generate hole trap-ups and interface states that cause reliability problems such as window-opening, charge loss, erratic erase and accentuating gate disturb. These interface states and trapped holes distribute themselves laterally from the source PN junction that is formed at the interface between the source and substrate and into the channel region of the cell. The peak density and the width of this trapped hole distribution depend upon both the junction bias and the control gate bias during the negative gate edge erase operation.
During a negative gate channel erase procedure, the electrons in the floating gate tunnel vertically through the tunnel oxide into the channel region of the cell. Since there is no electrical bias between the source region and the p-well region, there is no band-to-band current. However, other device reliability problems result. For example, since erasing is done along the channel region, interface generation and oxide trap-up are distributed along the entire length of the channel region. Such a concentration of interface states and oxide trap-up degrades the memory cell read current, which may in turn slow down the reading speed and eventually cause read errors. Trap-up at the portion of the oxide layer near the drain junction may also retard hot electron injection during programming. The amount of interface generation and oxide trap-up are dependent upon the peak electric field generated during the erase procedure.
Therefore, what is needed are methods of erasing memory cells that reduces the peak electric field across the tunnel oxide during erase without reducing the erase speed.